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ltc3828 3828f 1 high efficiency dual 2.5v/3.3v step-down converter with tracking features descriptio u applicatio s u typical applicatio u dual, 2-phase step-down controller with tracking dual, 180 phased controllers reduce required input capacitance and power supply induced noise tracking for both outputs constant frequency current mode control wide v in range: 4.5v to 28v operation power good output voltage indicator adjustable soft-start current ramping foldback output current limiting disabled at start-up no reverse current during soft-start interval clock output for 3-, 4-, 6-phase operation dual n-channel mosfet synchronous drive 1% output voltage accuracy phase-lockable fixed frequency 260khz to 550khz opti-loop ? compensation minimizes c out very low dropout operation: 99% duty cycle output overvoltage protection small 28-lead ssop and 5mm 5mm qfn packages the ltc ? 3828 is a dual high performance step-down switching regulator controller that drives all n-channel synchronous power mosfet stages. a constant fre- quency current mode architecture allows for a phase- lockable frequency of up to 550khz. the trckss pin provides both soft-start and tracking functions. multiple ltc3828s can be daisy-chained in applications requiring more than two voltages to be tracked. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the precision 0.8v reference and power good output indicator are compatible with a wide 4.5v to 28v (30v maximum) input supply range, encompassing all bat- tery chemistries. the run pins control their respective channels indepen- dently. the fcb/pllin pin selects among burst mode ? operation, skip-cycle mode and continuous current mode. current foldback limits mosfet dissipation during short- circuit conditions. reverse current and current foldback functions are disabled during soft-start. telecom infrastructure asic power supply industry equipment + 4.7 f 0.1 f 63.4k 1% 1000pf 3.2 h 220pf 1 f ceramic 22 f 50v ceramic + 47 f 4v sp 0.01 ? 20k 1% 20k 1% 15k 3.3v 5a 0.1 f 0.1 f 0.1 f 42.5k 1% 3.2 h 220pf 1000pf + 56 f 4v sp 0.01 ? 20k 1% 15k 2.5v 5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd sense1 + sense2 + sense1 C sense2 C v osense1 v osense2 i th1 i th2 v in pgood intv cc run1 run2 4.5v to 28v 3828 ta01 ltc3828 fcb/pllin 500khz trckss1 trckss1 trckss2 63.4k 1% , ltc and lt are registered trademarks of linear technology corporation. burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6304066, 6580258
2 ltc3828 3828f input supply voltage (v in )........................ 30v to C 0.3v top side driver voltages (boost1, boost2) .................................. 36v to C 0.3v switch voltage (sw1, sw2) ........................ 30v to C 5v intv cc, drv cc , run1, run2, (boost1-sw1), (boost2-sw2) .......................................... 7v to C 0.3v sense1 + , sense2 + , sense1 C , sense2 C voltages ....................... (1.1)intv cc to C 0.3v fcb/pllin, pllfltr, clkout, phsmd voltage .............................. intv cc to C 0.3v trckss1, trckss2 ........................... intv cc to C 0.3v absolute axi u rati gs w ww u package/order i for atio uu w (note 1) pgood ..................................................... 5.5v to C0.3v i th1, i th2 , v osense1 , v osense2 voltages ... 2.7v to C 0.3v peak output current <10 s (tg1, tg2, bg1, bg2) .. 3a intv cc peak output current ................................ 50ma operating temperature range (note 7) ltc3828e .......................................... C 40 c to 85 c junction temperature (note 2) ............................ 125 c storage temperature range ................ C 65 c to 125 c reflow peak body temperature (uh package) .... 260 c lead temperature (soldering, 10 sec) (gn package) ................................................... 300 c order part number LTC3828EUH t jmax = 125 c, ja = 34 c/w exposed pad is sgnd (pin 33), must be soldered to pcb the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run1, 2 = 5v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units main control loops v osense1, 2 regulated feedback voltage (note 3); i th1, 2 voltage = 1.2v 0.792 0.800 0.808 v i vosense1, 2 feedback current (note 3) 5 50 na v reflnreg reference voltage line regulation v in = 4.6v to 28v (note 3) 0.002 0.02 %/v v loadreg output voltage load regulation (note 3) measured in servo loop; ? i th voltage = 1.2v to 0.7v 0.1 0.5 % measured in servo loop; ? i th voltage = 1.2v to 2.0v C 0.1 C 0.5 % g m1, 2 transconductance amplifier g m i th1, 2 = 1.2v; sink/source 5ua; (note 3) 1.3 mmho consult ltc marketing for parts specified with wider operating temperature ranges. uh part marking 3828 order part number ltc3828eg t jmax = 125 c, ja = 95 c/w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 clkout pgood boost1 tg1 sw1 v in intv cc pgnd bg1 bg2 sw2 tg2 boost2 run2 trckss1 i th1 sense1+ sense1C v osense1 pllfltr run1 fcb/pllin sgnd trckss2 sense2 C sense2 + i th2 v osense2 32 31 30 29 28 27 26 25 9 10 11 12 13 top view 33 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 v osense1 pllfltr run1 phsmd fcb/pllin sgnd trckss2 nc sw1 v in intv cc drv cc pgnd bg1 bg2 sw2 sense1 C sense1 + i th1 trckss1 clkout pgood boost1 tg1 nc sense2 C sense2 + i th2 v osense2 run2 boost2 tg2 uh package 32-lead (5mm 5mm) plastic qfn
ltc3828 3828f 3 the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run1, 2 = 5v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units g mgbw1, 2 transconductance amplifier gbw i th1, 2 = 1.2v; (note 3) 3 mhz i q input dc supply current (note 4) normal mode v in = 15v; v out1 = 5v 2 3 ma shutdown v run/ss1, 2 = 0v 20 100 a v fcb forced continuous threshold 0.76 0.800 0.84 v i fcb forced continuous pin current v fcb = 0.85v C 0.50 C 0.18 C 0.1 a v binhibit burst inhibit (constant frequency) measured at fcb pin 4.3 4.8 v threshold uvlo undervoltage lockout v in ramping down 3.5 4 v v ovl feedback overvoltage lockout measured at v osense1, 2 0.84 0.86 0.88 v i sense sense pins total source current (each channel); v sense1 C , 2 C = v sense1 + , 2 + = 0v C 90 C 65 a df max maximum duty factor in dropout 98 99.4 % i trckss1,2 soft-start charge current 0.5 1.2 a v run1, 2 on run pin on threshold v run1, v run2 rising 1.0 1.5 2.0 v v sense(max) maximum current sense threshold v osense1, 2 = 0.7v,v sense1 C , 2 C = 5v 62 75 85 mv v osense1, 2 = 0.7v,v sense1 C , 2 C = 5v 60 75 88 mv tg transition time: (note 5) tg1, 2 t r rise time c load = 3300pf 55 100 ns tg1, 2 t f fall time c load = 3300pf 55 100 ns bg transition time: (note 5) bg1, 2 t r rise time c load = 3300pf 65 120 ns bg1, 2 t f fall time c load = 3300pf 55 100 ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 60 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver 80 ns t on(min) minimum on-time tested with a square wave (note 6) 120 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 30v 4.8 5.0 5.2 v v ldo int intv cc load regulation i cc = 0 to 20ma 0.2 2.0 % oscillator and phase-locked loop f nom nominal frequency v pllfltr = 1.2v 360 400 440 khz f low lowest frequency v pllfltr = 0v 230 260 290 khz f high highest frequency v pllfltr 2.4v 480 550 590 khz i pllfltr phase detector output current sinking capability f pllin < f osc C17 a sourcing capability f pllin > f osc 17 a pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level, either controller v osense with respect to set output voltage v osense ramping negative C 6 C7.5 C 9.5 % v osense ramping positive 6 7.5 9.5 %
4 ltc3828 3828f output current (a) 0.001 efficiency (%) 10 3828 g01 0.01 0.1 1 output current (a) 0.001 10 0.01 0.1 1 100 90 80 70 60 50 40 30 20 10 0 efficiency (%) 3828 g02 100 90 80 70 60 50 input voltage (v 5 efficiency (%) 100 90 80 70 60 50 25 3828 g03 10 15 20 30 temperature ( c) C50 3.8 3.6 3.4 3.2 3.0 100 3828 g06 C25 0 25 50 75 125 undervoltage lockout (v) intv cc voltage (v) 3828 g05 input voltage (v) 0 supply current ( a) 1200 1000 800 600 400 200 0 5.2 5.0 4.8 4.6 4.4 4.2 4.0 5101520 3828 g04 25 30 input voltage (v) 0 5 10 15 20 25 30 burst mode operation forced continuous mode constant frequency (burst disable) v out = 5v f = 260khz v in =15v v out = 5v f = 260khz v out = 5v i out = 3a f = 260khz v in = 7v v in = 20v v in = 15v both controllers on shutdown i load = 1ma note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc3828uh: t j = t a + (p d ? 34 c/w) ltc3828g: t j = t a + (p d ? 95 c/w) note 3: the ic is tested in a feedback loop that servos v ith1, 2 to a specified voltage and measures the resultant v osense1, 2. note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 5: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 6: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). note 7: the ltc3828e is guaranteed to meet performance specifications over the C40 c to 85 c operating temperature range as assured by design, characterization and correlation with statistical process controls. efficiency vs output current and mode (figure 14) efficiency vs output current (figure 14) efficiency vs input voltage (figure 14) typical perfor a ce characteristics uw electrical characteristics internal 5v ldo line regulation undervoltage lockout vs temperature supply current vs input voltage (figure 14) t a = 25 c unless otherwise noted.
ltc3828 3828f 5 temperature ( c) C50 700 600 500 400 300 200 100 0 25 75 3828 g07 C25 0 50 100 125 temperature ( c) C50 25 75 C25 0 50 100 125 temperature ( c) C50 25 75 C25 0 50 100 125 temperature ( c) C50 25 75 C25 0 50 100 125 temperature ( c) C50 25 75 C25 0 50 100 125 frequency (khz) trckss current ( a) 1.5 1.3 1.1 0.9 0.7 0.5 3828 g08 37 35 33 31 29 3828 g09 current sense input current ( a) v sense (mv) 80 78 76 74 72 70 3828 g10 v out = 5v 5.1 5.0 4.9 4.8 4.7 3828 g11 intv cc voltage (v) load current (a) 0 normalized v out (%) C0.2 C0.1 4 3828 g12 C0.3 C0.4 1 2 3 5 0 fcb = 0v v in = 15v figure 14 duty factor (%) 0 v sense (mv) 50 75 3828 g13 25 0 20 40 100 60 80 percent on nominal output voltage (%) 0 v sense (mv) 0.75 3828 g14 0.25 0.5 1.0 80 70 60 50 40 30 20 10 0 comm0n mode voltage (v) 0 v sense (mv) 70 75 4 3828 g15 65 60 1 2 3 5 80 v pllfltr = 2.4v v pllfltr = 1.2v v pllfltr = 0v oscillator frequency vs temperature trckss current vs temperature current sense pin input current vs temperature typical perfor a ce characteristics uw maximum current sense threshold vs temperature load regulation intv cc voltage vs temperature t a = 25 c unless otherwise noted. maximum current sense threshold vs duty factor maximum current sense threshold vs percent of nominal output voltage (foldback) maximum current sense threshold vs sense common mode voltage
6 ltc3828 3828f v ith (v) 0 v sense (mv) 80 70 60 50 40 30 20 10 0 C10 C20 2.0 3828 g16 3828 g19 3828 g20 3828 g21 3828 g22 3828 g23 3828 g24 0.5 1.0 1.5 2.5 output current (a) 0 dropout voltage (v) 4.0 3828 g17 1.0 0.5 1.5 2.5 3.5 2.0 3.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v sense common mode voltage (v) 01 i sense ( a) 24 3 5 6 3828 g18 100 50 0 C50 C100 v out1 1v/div v out2 1v/div v out1 100mv/div v out2 100mv/div i l1 2a/div v out1 100mv/div v out2 100mv/div sw1 20v/div i in 25a/div v in ripple 50mv/div sw2 20v/div i l1 2a/div v out1 1v/div v out2 1v/div v out1 1v/div v out2 1v/div 5ms/div 2ms/div 100 s/div 500ns/div 50 s/div 50 s/div v in = 12v v out1 = 5v v out2 = 3.3v v in = 12v v out1 = 5v v out2 = 3.3v load step = 0a to 3a with ratiometric tracking v in = 12v v out1 = 5v v out2 = 3.3v load step = 0a to 3a with ratiometric tracking v in = 12v v out1 = 5v v out2 = 3.3v i out5 = i out3.3 = 2a v in = 12v v out1 = 5v v out2 = 3.3v v in = 12v v out1 = 5v v out2 = 3.3v soft start-up: (figure 14, with coincident tracking) typical perfor a ce characteristics uw t a = 25 c unless otherwise noted. current sense threshold vs i th voltage dropout voltage vs output current (figure 14) sense pins total source current soft start-up: (figure 14, with internal soft start-up) soft start-up: (figure 14, with ratiometric tracking) load step: burst mode operation (figure 14) input source/capacitor instantaneous current (figure 14) load step: continuous mode (figure 14)
ltc3828 3828f 7 i th1, i th2 (pins 2, 13/pins 30, 12): error amplifier output and switching regulator compensation point. each asso- ciated channels current comparator trip point increases with this control voltage. phsmd (pin 4, qfn only): control input to phase selector which determines the phase relationship between control- ler 1, controller 2 and the clockout signal. v osense1 , v osense2 (pins 5, 14/pins 1, 13): error ampli- fier feedback input. receives the remotely-sensed feed- back voltage for each controller from an external resistive divider across the output. pllfltr (pin 6/pin 2): filter connection for phase- locked loop. alternatively, this pin can be driven with an ac or dc voltage source to vary the frequency of the internal oscillator. fcb/pllin (pin 8/pin 5): forced continuous control input and external synchronization input to phase detec- tor . pulling this pin below 0.8v will force continuous synchronous operation. feeding an external clock signal will synchronize the ltc3828 to the external clock. sgnd (pin 9/pin 6): small signal ground. common to both controllers, this pin must be routed separately from high current grounds to the common (C) terminals of the c out capacitors. uu u pi fu ctio s trckss2, trckss1 (pins 10, 1/pins 7, 29): soft-start and output voltage tracking inputs. when one channel is configured to be the master of two outputs a capacitor to ground at this pin sets the ramp rate. the slave channel tracks the output of the master channel by reproducing the v fb voltage of the master channel with a resistor divider and applying that voltage to its track pin. an internal 1.2 a soft-start current is always charging these pins. sense2 , sense1 (pins 11, 4/pins 10, 32): the (C) input to the differential current comparators. sense2 + , sense1 + (pins 12, 3/pins 11, 31): the (+) input to the differential current comparators. the i th pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold. run2, run1 (pins 15, 7/pins 14, 3): run control inputs. forcing run pins below 1v would shut down the circuitry required for that particular channel. forcing the run pins over 2v would turn on the ic. boost2, boost1 (pins 16, 26/pins 15, 26): bootstrapped supplies to the top side floating drivers. capacitors are connected between the boost and switch pins and schot- tky diodes are tied between the boost and intv cc pins. voltage swing at the boost pins is from intv cc to (v in + intv cc ). (ssop/qfn) typical perfor a ce characteristics uw 3828 g25 v out 20mv/div i l 1a/div 100 s/div v in = 12v v out = 5v v fcb = open i out = 20ma 3828 g26 v out 20mv/div i l 0.5a/div 2 s/div v in = 12v v out = 5v v fcb = 5v i out = 20ma burst mode operation (figure 14) constant frequency (burst inhibit) operation (figure 14) t a = 25 c unless otherwise noted.
8 ltc3828 3828f uu u pi fu ctio s tg2, tg1 (pins 17, 25/pins 16, 25): high current gate drives for top n-channel mosfets. these are the outputs of floating drivers with a voltage swing equal to intv cc C 0.5v superimposed on the switch node voltage sw. sw2, sw1 (pins 18, 24/pins 17, 24): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . bg2, bg1 (pins 19, 20/pins 18, 19): high current gate drives for bottom (synchronous) n-channel mosfets. voltage swing at these pins is from ground to intv cc . pgnd (pin 21/pin 20): driver power ground. connects to the sources of bottom (synchronous) n-channel mosfets, anodes of the schottky rectifiers and the (C) terminal(s) of c in . drv cc (pin 21 qfn only): external power input to gate drives. it can be connected with int vcc together and use int vcc as gate drives power supply. intv cc (pin 22/pin 22): output of the internal 5v linear low dropout regulator. the driver and control circuits are powered from this voltage source. must be decoupled to power ground with a minimum of 4.7 f tantalum or other low esr capacitor. v in (pin 23/pin 23): main supply pin. a bypass capacitor should be tied between this pin and the signal ground pin. pgood (pin 27/pin 27): open-drain logic output. pgood is pulled to ground when the voltage on either v osense pin is not within 7.5% of its set point. clkout (pin 28/pin 28): output clock signal available to daisychain other controller ics for additional mosfet driver stages/phases. nc (pins 8, 9 qfn only) : these no connect pins are not tied internally to anything. on the pc layout, these pin landings should be connected to the sgnd plane under the ic. exposed pad (pin 33, qfn only) : signal ground. must be soldered to the pcb, providing a local ground for the control components of the ic, and be tied to the pgnd pin under the ic.
ltc3828 3828f 9 fu ctio al diagra u u w switch logic C + 5v v in 4.5v binh clk2 clk1 0.18 a + C fcb + C C + 0.8v v ref internal supply r lp c lp 3v fcb/pllin intv cc sgnd (uh package pad) + 5v ldo reg sw shdn 0.55v top boost tg c b c in d 1 d b pgnd bot bg drv cc drv cc v in + c out v out 3828 fd/f01 r sense + v osense drop out det run soft start bot top on s r q q oscillator phase det pllfltr clkout fcb ea 0.86v 0.80v ov v fb 6v r1 C + r2 r c 4(v fb ) rst shdn run i th c c c c2 4(v fb ) 0.86v slope comp 3mv + C C + sense C sense + intv cc 30k 45k 2.4v 45k 30k 100k ? i1 i2 b duplicate for second controller channel c ss + C C + phase logic phsmd + C + C + C + C pgood v osense1 v osense2 0.86v 0.74v 0.86v 0.74v pll detector trckss 1.2 a drv cc figure 1
10 ltc3828 3828f (refer to functional diagram) operatio u main control loop the ic uses a constant frequency, current mode step- down architecture with the two controller channels oper- ating 180 degrees out of phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i 1 , resets the rs latch. the peak inductor current at which i 1 resets the rs latch is con- trolled by the voltage on the i th pin, which is the output of each error amplifier ea. the v osense pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current in- creases, it causes a slight decrease in v osense relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current compara- tor i 2 , or the beginning of the next cycle. the top mosfet drivers are biased from floating boot- strap capacitor c b , which normally is recharged during each off cycle through an external diode when the top mosfet turns off. as v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector de- tects this and forces the top mosfet off for about 400ns every tenth cycle to allow c b to recharge. the main control loop is shut down by pulling the run pin low. when the run pin reaches 1.5v, the main control loop is enabled. when run1 is low, all controller functions are shut down, including the 5v regulator. low current operation the fcb/pllin pin is a multifunction pin providing two functions: 1) to accept external clock signal; and 2) to select among three modes of light load operations. when the fcb/pllin pin voltage is below 0.8v, the controller forces continuous pwm current mode operation. in this mode, the top and bottom mosfets are alternately turned on to maintain the output voltage independent of direction of inductor current. when the fcb/pllin pin is below v intvcc C 2v but greater than 0.8v, the controller enters burst mode operation. burst mode operation sets a minimum output current level before inhibiting the top switch and turns off the synchronous mosfet(s) when the inductor current goes negative. this combination of requirements will, at low currents, force the i th pin below a voltage threshold that will temporarily inhibit turn-on of both output mosfets until the output voltage drops. there is 60mv of hysteresis in the burst comparator b tied to the i th pin. this hysteresis produces output signals to the mosfets that turn them on for several cycles, followed by a variable sleep interval depending upon the load current. the resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. when the fcb/pllin pin voltage is above 4.8v, the controller operates in constant frequency mode and the synchro- nous mosfet is turned off when inductor current nears zero in each cycle. in order to prevent erratic operation if no external connec- tions are made to the fcb/pllin pin, the fcb/pllin pin has a 0.18 a internal current source pulling the pin high. the following table summarizes the possible states avail- able on the fcb/pllin pin: table 1 fcb/pllin pin condition 0v to 0.75v forced continuous both controllers (current reversal allowed burst inhibited) 0.85v < v fcb/pllin < 4.3v minimum peak current induces burst mode operation no current reversal allowed >4.8v burst mode operation disabled constant frequency mode enabled no current reversal allowed no minimum peak current besides providing a logic input to force continuous operation, the fcb/pllin pin acts as the input for exter- nal clock synchronization. upon detecting the presence of an external clock signal, channel 1 will lock on to this external clock and this will be followed by channel 2 (see frequency synchronization section). the ltc3828 de- faults to forced continuous mode when sychronized to an external clock.
ltc3828 3828f 11 inductor current) operation over the widest possible out- put current range. this constant frequency operation is not as efficient as burst mode operation, but does provide a lower noise, constant frequency operating mode down to approximately 1% of the designed maximum output current. continuous current (pwm) operation tying the fcb/pllin pin to ground will force continuous current operation. this is the least efficient operating mode, but may be desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levelsbeware! output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>7.5%) as well as other more serious condi- tions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good (pgood) pin the pgood pin is connected to an open drain of an internal mosfet. the mosfet turns on and pulls the pin low when either output is not within 7.5% of the nominal output level as determined by the resistive feedback divider. when both outputs meet the 7.5% requirement, the mosfet is turned off within 10 s and the pin is allowed to be pulled up by an external resistor to a source of up to 5.5v. foldback current foldback current limiting is activated when the output voltage falls below 70% of its nominal level. if a short is present, a safe, low output current is provided due to internal current foldback and actual power wasted is low due to the efficient nature of the current mode switching regulator. this function is disabled at start-up. (refer to functional diagram) frequency synchronization the phase-locked loop allows the internal oscillator to be synchronized to an external source via the fcb/pllin pin. the output of the phase detector at the pllfltr pin is also the dc frequency control input of the oscillator that operates over a 260khz to 550khz range corresponding to a dc voltage input from 0v to 2.4v. when locked, the pll aligns the turn on of the top mosfet to the rising edge of the synchronizing signal. the internal master oscillator runs at a frequency twelve times that of each controllers frequency. the phsmd pin (uh package only) determines the relative phases be- tween the internal controllers as well as the clkout signal as shown in table 2. the phases tabulated are relative to zero phase being defined as the rising edge of the top gate (tg1) driver output of controller 1. table 2. v phsmd gnd open intv cc controller 1 0 0 0 controller 2 180 180 240 clkout 60 90 120 the clkout signal can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or separate outputs. input capacitance esr requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the rms current squared. a two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required rms current rating of the input capacitor(s). in the g28 package, clkout is 90 out of phase with channel 1 and channel 2. constant frequency operation when the fcb/pllin pin is tied to intv cc , burst mode operation is disabled and the forced minimum output current requirement is removed. this provides constant frequency, discontinuous current (preventing reverse operatio u
12 ltc3828 3828f theory and benefits of 2-phase operation the ltc3728 and the ltc3828 family of dual high effi- ciency dc/dc controllers brings the considerable benefits of 2-phase operation to portable applications for the first time. notebook computers, pdas, handheld termi- nals and automotive electronics will all benefit from the lower input filtering requirement, reduced electromag- netic interference (emi) and increased efficiency associ- ated with 2-phase operation. why the need for 2-phase operation? up until the 2-phase family, constant-frequency dual switching regulators op- erated both channels in phase (i.e., single-phase opera- tion). this means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. these large amplitude current pulses increased the total rms current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both emi and losses in the input capacitor and battery. with 2-phase operation, the two channels of the dual- switching regulator are operated 180 degrees out of phase. this effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. the result is a significant reduc- tion in total rms input current, which in turn allows less expen sive input capacitors to be used, reduces shielding requirements for emi and improves real world operating efficiency. figure 2 compares the input waveforms for a representa- tive single-phase dual switching regulator to the ltc3828 2-phase dual switching regulator. an actual measurement of the rms input current under these conditions shows that 2-phase operation dropped the input current from 2.6a rms to 1.9a rms . while this is an impressive reduction in itself, remember that the power losses are proportional to i rms 2 , meaning that the actual power wasted is reduced by a factor of 1.86. the reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resis- tances and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. of course, the improvement afforded by 2-phase opera- tion is a function of the dual switching regulators relative duty cycles which, in turn, are dependent upon the input voltage v in (duty cycle = v out /v in ). figure 3 shows how the rms input current varies for single-phase and 2-phase operation for 3.3v and 5v regulators over a wide input voltage range. it can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, but in fact extend over a wide region. a good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. (refer to functional diagram) operatio u (b) (a) 5v switch 20v/div 3.3v switch 20v/div i in(meas) = 1.9a rms dc236 f02b i in(meas) = 2.6a rms dc236 f02a figure 2. input waveforms comparing single-phase (a) and 2-phase (b) operation for dual switching regulators converting 12v to 5v and 3.3v at 3a each. the reduced input ripple with the ltc3828 2-phase regulator allows less expensive input capacitors, reduces shielding requirements for emi and improves efficiency input current 5a/div input voltage 100mv/div i n(meas) = 2.6a rms i n(meas) = 1.9a rms
ltc3828 3828f 13 (refer to functional diagram) operatio u time (4a) coincident tracking v out1 v out2 output voltage time 3828 f04 (4b) ratiometric tracking v out1 v out2 output voltage figure 4. two different modes of output voltage tracking applicatio s i for atio wu uu input voltage (v) 0 input rms current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 10 20 30 40 3828 f03 single phase dual controller 2-phase dual controller v o1 = 5v/3a v o2 = 3.3v/3a figure 3. rms input current comparison output voltage tracking the ltc3828 allows the user to program how the channel outputs ramp up and down by means of the trckss pins. through these pins, the channel outputs can be set up to either coincidentally or ratiometrically tracking, as shown in figure 4. the trckss pins act as clamps on the channels refer- ence voltages. v out is referenced to the trckss voltage when the trckss < 0.8v and to the internal precision reference when trckss > 0.8v. to implement the tracking in figure 4a, connect an extra resistive divider to the output of the master channel and connect its midpoint to the slave channels trckss pin. the ratio of this divider should be selected the same as that of channel 2s feedback divider (figure 5). in this tracking mode, the master channel? output must be set higher than slave channel? output . to implement the ratiomet- ric tracking in figure 4b, no extra divider is needed; simply connect one of trckss pins to the other channels v fb pin (figure 5).
14 ltc3828 3828f applicatio s i for atio wu u u figure 5. setup for coincident and ratiometric tracking r3 r1 r4 r2 r3 v out2 r4 (5a) coincident tracking setup to v osense1 pin to trckss2 pin to v osense2 pin v out1 r1 r2 r3 v out2 r4 3828 f05 (5b) ratiometric tracking setup to v osense1 pin to trckss2 pin to v osense2 pin v out1 figure 6. equivalent input circuit of error amplifier of channel 2 figure 7. alternative setup for coincident tracking C + ii d1 trckss 0.8v v osense d2 d3 3828 f06 ea s1 r1 r4 v out1 v out2 to trckss2 pin to v osense1 pin to v osense2 pin r2 r5 r3 3828 f07 r r vr r v out out 1 208 1 3 408 1 12 == ? ? ? ? ? ? . C, . C rr r vr rr r r v out out 12 308 1 1 23 4 508 1 12 + = + == ? ? ? ? ? ? . C, . C by selecting different resistors, the ltc3828 can achieve different modes of tracking including the two in figure 4. figure 6 helps to explaining the tracking function. at the input stage of an error amplifier, two diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. the top two current sources are of the same value. when the trckss voltage is low, switch s1 is on and v osense follows the trckss voltage. when the trckss voltage is close to 0.8v, the reference voltage, switch s1, is off and v osense follows the reference voltage. the regulation for both channels outputs are not affected by the tracking mode. in the ratiometric tracking mode, the two channels do not exhibit cross talk. the number of resistors in figure 5a can be further reduced with the scheme in figure 7. in a system that requires more than two tracked supplies, multiple ltc3828s can be daisy-chained through the trckss1 pin. trckss1 clamps channel 1s reference in the same manner trckss2 clamps channel 2. to elimi- nate the possibility of multiple ltc3828s coming on at different times, only the master ltc3828s trckss1 pin should be connected to a soft-start capacitor. figure 8 shows the circuit with four outputs. three of them are programmed in the coincident mode while the fourth one tracks ratiometrically. if output tracking is not needed, the trckss pins are used as soft start-up pins. the capaci- tors connected to those pins set the soft-start ramping up speed. figure 15 is a basic ltc3828 application circuit. external component selection is driven by the load requirement, and begins with the selection of r sense and the inductor value. next, the power mosfets and d1 are selected. finally, c in and c out are selected. the circuit shown in figure 15 is configured for operation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense is chosen based on the required output current. the current comparator has a maximum threshold of 75mv/r sense and an input common mode range of sgnd to 1.1(intv cc ). the current comparator threshold sets the
ltc3828 3828f 15 figure 8. four outputs with tracking and ratiometric sequencing v osense1 c ss r3 r1 r2 r5 v out1 r2 r4 r2 r2 v osense2 v out2 r5 r2 v out4 r4 r2 v out3 trckss1 trckss2 ltc3828 master trckss1 v osense1 v osense2 trckss2 ltc3828 slave (8a) circuit setup time 3828 f08 (8b) output voltage v out1 v out3 v out4 v out2 output voltage applicatio s i for atio wu uu r r vr r vr r vr r v out out out out 1 208 1 3 208 1 4 208 1 5 208 1 123 4 === = ? ? ? ? ? ? . C, . C . C, . C peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, ? i l . allowing a margin for variations in the ic and external component values yields: r mv i sense max = 50 when using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability crite- rion for buck regulators operating at greater than 50% duty factor. a curve is provided to estimate this reduction in peak output current level depending upon the operating duty factor. operating frequency the ic uses a constant frequency phase-lockable architec- ture with the frequency determined by an internal capaci- tor. this capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the pllfltr pin. refer to phase-locked loop and frequency synchronization in the applications infor- mation section for additional information. a graph for the voltage applied to the pllfltr pin vs frequency is given in figure 9. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum switching frequency is approximately 550khz. figure 9. pllfltr pin voltage vs frequency operating frequency (khz) 200 300 400 500 600 pllfltr pin voltage (v) 3828 f09 2.5 2.0 1.5 1.0 0.5 0 inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of
16 ltc3828 3828f applicatio s i for atio wu uu mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current ? i l decreases with higher induc- tance or frequency and increases with higher v in : ? i fl v v v l out out in = ? ? ? ? ? ? 1 1 ()( ) C accepting larger values of ? i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ? i l =0.3(i max ). the maximum ? i l occurs at the maximum input voltage. the inductor value also has secondary effects. the transi- tion to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher ? i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor selection usually, high inductance is preferred for small current ripple and low core loss. unfortunately, increased induc- tance requires more turns of wire or small air gap of the inductor, resulting in high copper loss or low saturation current. once the value of l is known, the actual inductor must be selected. there are two popular types of core material of commercial available inductors. ferrite core inductors usually have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. however, ferrite core saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. one advantage of the ltc3828 is its current mode control that detects and limits cycle-by-cycle peak inductor current. therefore, accurate and fast protection is achieved if the inductor is saturated in steady state or during transient mode. powder iron inductors usually saturate soft, which means the inductance drops in a linear fashion when the current increases. however, the core loss of the powder iron inductor is usually higher than the ferrite inductor. so design with high switching frequency should pay atten- tion to the inductor core loss too. inductor manufacturers usually provide inductance, dcr, (peak) saturation current and (dc) heating current ratings in the inductor data sheet. a good supply design should not exceed the saturation and heating current rating of the inductor. power mosfet and d1 selection two external power mosfets must be selected for each controller in the ltc3828: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up. consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , miller capacitance c miller , input volt- age and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v out in =
ltc3828 3828f 17 applicatio s i for atio wu uu synchronous switch duty cycle vv v in out in = C the mosfet power dissipations at maximum output current are given by: p v v ir v i rc vvv f main out in max ds on in max dr miller intvcc thmin thmin = () + () + () ? ? ? ? ? ? ()( ) + ? ? ? ? ? ? () 2 2 1 2 11 () ? C p vv v ir sync in out in max ds on = () + () C () 2 1 where is the temperature dependency of r ds(on) and r dr (approximately 2 ? ) is the effective driver resistance at the mosfets miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 12v the high current efficiency generally improves with larger mosfets, while for v in 12v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/ c can be used as an approximation for low voltage mosfets. the schottky diode d1 shown in figure 1 conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead- time and requiring a reverse recovery period that could cost efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. c in and c out selection the selection of c in is simplified by the multiphase archi- tecture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst case rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms current requirement. increasing the output current, drawn from the other out-of-phase controller, will actually decrease the input rms ripple current from this maximum value (see figure 3). the out-of-phase technique typically re- duces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. the type of input capacitor, value and esr rating have efficiency effects that need to be considered in the selec- tion process. the capacitance value chosen should be sufficient to store adequate charge to keep high peak battery currents down. 20 f to 40 f is usually sufficient for a 25w output supply operating at 260khz. the esr of the capacitor is important for capacitor power dissipation as well as overall battery efficiency. all of the power (rms ripple current ? esr) not only heats up the capacitor but wastes power from the battery. medium voltage (20v to 35v) ceramic, tantalum, os-con and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramic voltage coefficients are very high and may have audible piezoelec- tric effects; tantalums need to be surge-rated; os-cons suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics higher esr and dryout possibility require several to be used. multiphase systems allow the lowest amount of capacitance overall. as little as one 22 f or two to three 10 f ceramic capaci- tors are an ideal choice in a 20w to 35w power supply due to their extremely low esr. even though the capacitance at 20v is substantially below their rating at zero-bias, very low esr loss makes ceramics an ideal candidate for
18 ltc3828 3828f applicatio s i for atio wu uu highest efficiency battery operated systems. also con- sider parallel ceramic and high quality electrolytic capaci- tors as an effective means of achieving esr and bulk capacitance goals. in continuous mode, the source current of the top n-chan- nel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c quiredi i vvv v in rms max out in out in re / ? () [] 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. the benefit of the ltc3828 multiphase clocking can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the interleaving of current pulses through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. remember that input protection fuse resistance, battery resistance and pc board trace resis- tance losses are also reduced due to the reduced peak currents in a multiphase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. the drains of the two top mosfets should be placed within 1cm of each other and share a common c in (s). separating the drains and c in may pro- duce undesirable voltage and current resonances at v in . the selection of c out is driven by the required output voltage ripple and load transient response. both the ca- pacitor effective series resistance (esr) and capacitance determine the output ripple: ? v i esr fc out l out ? + ? ? ? ? ? ? ? 1 8 where f = operating frequency, c out = output capacitance and ? i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. usually, ceramic capacitors are used to minimize the output voltage ripple because of their ultralow esr. cur- rently, multilayer ceramic capacitors have capacitor val- ues up to hundreds of f. however, the capacitance of the ceramic capacitors usually decreases with increased dc bias voltage and ambient temperature. in general, x5r or x7r type capacitors are recommended for high perfor- mance solutions. the opti-loop current mode control of ltc3828 provides stable, high performance transient response even with all ceramic output capacitors. manu- factures such as tdk, taiyo yuden, murata and avx provide high performance ceramic capacitors. when high capacitance is needed, especially for load transient requirement, low esr polymerized electrolytic capacitors such as sanyo poscap or panasonic sp capacitor can be used in parallel with ceramic capacitors. other high performance electolytic capacitor manufactur- ers include avx, kemet and nec. with ltc3828, a combination of ceramic and low esr electrolytic capaci- tors can provide a low ripple, fast transient, high density and cost-effective solution. consult manufacturers for specific recommendations. intv cc regulator an internal p-channel low dropout regulator produces 5v at the intv cc pin from the v in supply pin. intv cc powers the drivers and internal circuitry within the ic. the intv cc pin regulator can supply a peak current of 50ma and must be bypassed to ground with a minimum of 4.7 f tantalum, 10 f special polymer, or low esr type electro- lytic capacitor. a 1 f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly
ltc3828 3828f 19 applicatio s i for atio wu uu vv r r out =+ ? ? ? ? ? ? 08 1 2 1 . where r1 and r2 are defined in figure 1. sense + /sense pins the common mode input range of the current comparator sense pins is from 0v to (1.1)intv cc . continuous linear operation is guaranteed throughout this range allowing output voltage setting from 0.8v to 7.7v. a differential npn input stage is biased with internal resistors from an internal 2.4v source as shown in the functional diagram. this requires that current either be sourced or sunk from the sense pins depending on the output voltage. if the output voltage is below 2.4v current will flow out of both sense pins to the main output. the output can be easily preloaded by the v out resistive divider to compensate for the current comparators negative input bias current. the maximum current flowing out of each pair of sense pins is: i sense + + i sense C = (2.4v C v out )/24k since v osense is servoed to the 0.8v reference voltage, we can choose r1 in figure 1 to have a maximum value to absorb this current. rk v vv max out 124 08 24 () . .C = ? ? ? ? ? ? for v out < 2.4v regulating an output voltage of 1.8v, the maximum value of r1 should be 32k. note that for an output voltage above 2.4v, r1 has no maximum value necessary to absorb the sense currents; however, r1 is still bounded by the v osense feedback current. run and soft-start the ltc3828 run pins shut down their respective chan- nels independently. the ltc3828 is put in a low quiescent current state (i q < 30ua) if both run pin voltages are below 1v. trckss pins are actively pulled to ground in this shutdown state. once the run pin voltages are above 1.5v, the respective channel of the ltc3828 is powered recommended. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between channels. higher input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ic to be ex- ceeded. the system supply current is normally dominated by the gate charge current. additional external loading of the intv cc also needs to be taken into account for the power dissipation calculations. the absolute maximum rating for the intv cc pin is 50ma. to prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum v in . topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the exter- nal schottky diode must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. output voltage the output voltages are each set by an external feedback resistive divider carefully placed across the output capaci- tor. the resultant feedback signal is compared with the internal precision 0.800v voltage reference by the error amplifier. the output voltage is given by the equation:
20 ltc3828 3828f applicatio s i for atio wu uu up. the ltc3828 has the ability to either soft-start by itself with an external soft-start capacitor or tracking the output of the other channel or supply. when the device is config- ured to soft-start by itself, an external soft-start capacitor should be connected to the trckss pin. a soft-start current of 1.2 a is to charge the soft-start capacitor c ss . note that soft-start during this mode is achieved not by limiting the maximum output current of the controller but by controlling the ramp rate of the output voltage. as a matter of fact, current foldback is defeated during soft- start or tracking. during this phase, the ltc3828 is basically ramping the reference voltage until this voltage is 7.5% below the 0.8v reference. the total soft-start time can be estimated as: t soft-start = 0.925 ? 0.8v ? c ss /1.2 a the ltc3828 is designed such that the trckss pin is not actively pulled down if only one of the channels is shut down. in this case, the trckss pin voltage could be higher than 0.8v. if this particular channel is powered up again, the soft-start for this particular channel is provided by an internal soft-start timer about 450 s. the internal soft-start timer will also be in effect if the ltc3828 is trying to track an output supply that is already powered up. in any case, the force continuous mode is disabled and pgood signal is forced low during the first 90% of the soft-start phase. this time can be estimated for external soft-start as: t force = 0.9 ? 0.925 ? 0.8v ? c ss /1.2 a for internal soft-start, it will be 450 s. fault conditions: current limit and current foldback the current comparators have a maximum sense voltage of 75mv resulting in a maximum mosfet current of 75mv/r sense . the maximum value of current limit gener- ally occurs with the largest v in at the highest ambient temperature, conditions that cause the highest power dissipation in the top mosfet. each controller includes current foldback to help further limit load current when the output is shorted to ground. if the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 75mv to 25mv. under short-circuit conditions with very low duty cycles, the controller will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time t on(min) of each controller (typically 200ns), the input voltage and inductor value: ? i l(sc) = t on(min) (v in /l) the resulting short-circuit current is: i mv r i sc sense lsc = 25 1 2 C () ? fault conditions: overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the controller is operating. a comparator monitors the output for overvoltage condi- tions. the comparator (ov) detects overvoltage faults greater than 7.5% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvolt- age condition is cleared. the output of this comparator is only latched by the overvoltage condition itself and will therefore allow a switching regulator system having a poor pc layout to function while the design is being debugged. the bottom mosfet remains on continuously for as long as the ov condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regu- late properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. phase-locked loop and frequency synchronization the ic has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. this allows the top mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 50% around the center
ltc3828 3828f 21 applicatio s i for atio wu uu frequency f o . a voltage applied to the pllfltr pin of 1.2v corresponds to a frequency of approximately 400khz. the nominal operating frequency range of the ic is 260khz to 550khz. the phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. this type of phase detec- tor will not lock up on input frequencies close to the harmonics of the vco center frequency. the pll hold-in range, ? f h , is equal to the capture range, ? f c: ? f h = ? f c = 0.5 f o (260khz-550khz) the output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the pllfltr pin. if the external frequency (f pllin ) is greater than the oscil- lator frequency f 0sc , current is sourced continuously, pulling up the pllfltr pin. when the external frequency is less than f 0sc , current is sunk continuously, pulling down the pllfltr pin. if the external and internal fre- quencies are the same but exhibit a phase difference, the current sources turn on for an amount of time correspond- ing to the phase difference. thus the voltage on the pllfltr pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase comparator output is open and the filter capacitor c lp holds the voltage. the ics fcb/pllin pin must be driven from a low impedance source such as a logic gate located close to the pin. when using multiple ics for a phase-locked system, the pllfltr pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the masters frequency. a dc voltage of 0.7v to 1.7v applied to the master oscillators pllfltr pin is recom- mended in order to meet this requirement. the resultant operating frequency can range from 300khz to 500khz. the loop filter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp =10k ? and c lp is 0.01 f to 0.1 f. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that each controller is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t v vf on min out in () () < if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for each controller is approximately 200ns. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 300ns. this is of particular concern in forced continuous applica- tions with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. voltage positioning voltage positioning can be used to minimize peak-to-peak output voltage excursions under worst-case transient loading conditions. the open-loop dc gain of the control loop is reduced depending upon the maximum load step specifications. voltage positioning can easily be added to either or both controllers by loading the i th pin with a resistive divider having a thevenin equivalent voltage source equal to the midpoint operating voltage range of the error amplifier, or 1.2v (see figure 10). i th r c r t1 intv cc c c 3828 f10 ltc3828 r t2 figure 10. active voltage positioning applied to the ltc3828
22 ltc3828 3828f applicatio s i for atio wu uu the resistive load reduces the dc loop gain while main- taining the linear control range of the error amplifier. the maximum output voltage deviation can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. a complete explanation is included in design solutions 10. (see www.linear.com) efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3828 circuits: 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current has two components: the first is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents; v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg =f(q t +q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resistor, and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approxi- mately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m ? , r l = 50m ? , r sense = 10m ? and r esr = 40m ? (sum of both input and output capacitance losses), then the total resistance is 130m ? . this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = v in () ? ? ? ? ? ? () ()() + ? ? ? ? ? ? 2 2 1 5 1 ?? C i r cf vv v max dr miller th th other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very impor- tant to include these system level losses during the de- sign phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20 f to 40 f of capacitance having a maximum of 20m ? to 50m ? of esr. the ltc3828 2-phase architecture typically halves this input capacitance requirement over competing solu- tions. other losses including schottky conduction losses during dead-time and inductor core losses generally ac- count for less than 2% total additional loss.
ltc3828 3828f 23 applicatio s i for atio wu uu checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ? i load (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti- loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response . assuming a pre- dominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 15 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1 s to 10 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. but before you connect, be advised: you are plugging into the supply from hell. the main power line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-bat- tery. load-dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 11 is the most straightfor- ward approach to protect a dc/dc converter from the ravages of an automotive power line. the series diode
24 ltc3828 3828f applicatio s i for atio wu uu prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the ltc3828 have a maximum input voltage of 30v, most applications will also be limited to 30v by the mosfet bvd ss . the r sense resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: r mv a sense ?? 60 584 001 . . since the output voltage is below 2.4v the output resistive divider will need to be sized to not only set the output voltage but also to absorb the sense pins specified input current. rk v vv k v vv k max out 124 08 24 24 08 24 18 32 () . .C . .C. = ? ? ? ? ? ? = ? ? ? ? ? ? = choosing 1% resistors: r1 = 25.5k and r2 = 32.4k yields an output voltage of 1.816v. the power dissipation on the top side mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035 ? /0.022 ? , c miller = 215pf. at maximum input voltage with t(estimated) = 50 c: p v v cc v a pf khz mw main = () + [] ? () + () ? ? ? ? ? ? ? ()( ) + ? ? ? ? ? ? () = 18 22 5 1 0 005 50 25 0 035 22 5 2 4 215 1 523 1 23 300 332 2 2 . ( . )( C ) ? .? C. . a short-circuit to ground will result in a folded back current of: i mv ns v h a sc = ? ? ? ? ? ? ? = 25 001 1 2 120 22 33 21 . C () . . figure 11. automotive application protection v in 3828 f11 ltc3828 transient voltage suppressor general instrument 1.5ka24a 50a i pk rating 12v design example as a design example for one channel, assume v in = 12v(nominal), v in = 22v(max), v out = 1.8v, i max = 5a, and f = 300khz. the inductance value is chosen first based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the pllfltr pin to a resistive divider from the intv cc pin, generating 0.7v for 300khz operation. the minimum inductance for 30% ripple current is: ? i v fl v v l out out in = ? ? ? ? ? ? ()( ) C 1 a 4.7 h inductor will produce 23% ripple current and a 3.3 h will result in 33%. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.84a, for the 3.3 h value. increasing the ripple current will also help ensure that the minimum on-time of 100ns is not violated. the minimum on-time occurs at maximum v in : t v vf v v khz ns on min out in max () () . () == = 18 22 300 273
ltc3828 3828f 25 applicatio s i for atio wu uu with a typical value of r ds(on) and = (0.005/ c)(20) = 0.1. the resulting power dissipated in the bottom mosfet is: p vv v a mw sync = ()( ) ? () = 22 1 8 22 2 1 1 125 0 022 100 2 C. ... which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 ? for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr ( ? i l ) = 0.02 ? (1.67a) = 33mv pCp pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 12. the figure 13 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continu- ous mode. check the following in your layout: 1. are the top n-channel mosfets m1 and m3 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the ltc3828 v osense pins resistive dividers con- nect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the r2 and r4 connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1 f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the opposites channels voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3828 and occupy minimum pc trace area. 7. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging
26 ltc3828 3828f figure 12. ltc3828 recommended printed circuit layout diagram trckss1 i th1 sense1 + sense1 C v osense1 pllfltr run1 fcb/pllin sgnd trckss2 sense2 C sense2 + i th2 v osense2 clkout pgood boost1 tg1 sw1 v in intv cc pgnd bg1 bg2 sw2 tg2 boost2 run2 ltc3828 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 f in c b1 c b2 c intvcc c vin c in r in v in pgood r pu v pull_up <5.5v r sense1 l1 r sense2 l2 m1 m2 m3 m4 c out2 v out2 v out1 c out1 d1 d2 r1 r2 r3 r4 3828 f12 applicatio s i for atio wu uu
ltc3828 3828f 27 applicatio s i for atio wu uu figure 13. branch current waveforms r l1 d1 l1 sw1 r sense1 v out1 c out1 + v in ceramic c in r in + r l2 d2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3728 f11 r sense2 v out2 c out2 + ceramic
28 ltc3828 3828f applicatio s i for atio wu uu start with one controller on at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the appli- cation. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresh- oldtypically 10% to 20% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb imple- mentation. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. over- compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current com- parator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the under- voltage lockout circuit by further lowering v in while moni- toring the outputs to verify operation. investigate whether any problems exist only at higher output currents or only at higher input voltages. if prob- lems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are en- countered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate com- mon ground path voltage pickup between these compo- nents and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage.
ltc3828 3828f 29 applicatio s i for atio wu uu figure 14. ltc3828 high efficiency low noise 5v/3a, 3.3v/5a, regulator with ratiometric tracking trckss1 i th1 sense1 + sense1 C v osense1 pllfltr run1 fcb/pllin sgnd trckss2 sense2 C sense2 + i th2 v osense2 clkout pgood boost1 tg1 sw1 v in intv cc pgnd bg1 bg2 sw2 tg2 boost2 run2 ltc3828eg 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 f in c b1 0.22 f c b2 0.22 f c intvcc 4.7 f c vin 0.1 f c in 22 f 50v r in 10 ? pgood r pu v pull_up <5.5v r sense1 0.015 ? l1 4.7 h r sense2 0.01 ? l2 4.7 h m1 m2 m3 m4 c out2 180 f 4v c out1 150 f 6.3v v out2 3.3v 5a v out1 5v 3a v in 7v to 28v d1 d2 r1 20k 1% r2 105k 1% r3 20k 1% r4 63.4k 1% 3828 f14 33pf 33pf 180pf 180pf 1000pf 0.1 f 1000pf 15k 15k 158k 30k 1 f 1 f ceramic 1 f ceramic 2nf 10 ? 10 ? 2nf 10 ? 10 ?
30 ltc3828 3828f figure 15. ltc3828 high efficiency low noise 1.5v/7a, 3.3v/7a, 500khz regulator with ratiometric tracking trckss1 i th1 sense1 + sense1 C v osense1 pllfltr run1 fcb/pllin sgnd trckss2 sense2 C sense2 + i th2 v osense2 clkout pgood boost1 tg1 sw1 v in intv cc pgnd bg1 bg2 sw2 tg2 boost2 run2 ltc3828eg 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 f in c b1 0.22 f c b2 0.22 f c intvcc 4.7 f c vin 0.1 f c in 22 f 16v r in 10 ? pgood r pu v pull_up <5.5v r sense1 6m ? l1 0.68 h r sense2 6m ? l2 1 h m1 m2 m3 m4 c out2 220 f 4v c out1 330 f 2.5v v out2 3.3v 7a v out1 1.5v 7a v in 12v d1 d2 r1 20k 1% r2 17.4k 1% r3 20k 1% r4 63.4k 1% 3828 f14 33pf 33pf 180pf 500khz 180pf 1000pf 0.1 f 1000pf 15k 4.7k 26.1k 30k 1 f 1 f ceramic 1 f ceramic 2nf 10 ? 10 ? 2nf 10 ? 10 ? applicatio s i for atio wu uu
ltc3828 3828f 31 u package descriptio uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693) (for purposes of clarity, drawings are not to scale) 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated pin 1 top mark 0.40 0.10 31 1 2 32 bottom viewexposed pad 3.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.23 0.05 (uh) qfn 0102 0.50 bsc 0.200 ref 0.00 C 0.05 0.57 0.05 3.45 0.05 (4 sides) 4.20 0.05 5.35 0.05 0.23 0.05 package outline 0.50 bsc recommended solder pad layout information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. g28 ssop 0204 0.09 C 0.25 (.0035 C .010) 0 C 8 0.55 C 0.95 (.022 C .037) 5.00 C 5.60** (.197 C .221) 7.40 C 8.20 (.291 C .323) 1234 5 6 7 8 9 10 11 12 14 13 9.90 C 10.50* (.390 C .413) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 C 0.38 (.009 C .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 C 5.7 7.8 C 8.2 recommended solder pad layout 1.25 0.12 g package 28-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640)
32 ltc3828 3828f part number description comments ltc1628/ltc1628-pg/ 2-phase, dual output synchronous step-down reduces c in and c out , power good output signal, synchronizable, ltc1628-sync dc/dc controller 3.5v v in 36v, i out up to 20a, 0.8v v out 5v ltc1629/ 20a to 200a polyphase tm synchronous controllers expandable from 2-phase to 12-phase, uses all ltc1629-pg surface mount components, no heat sink, v in up to 36v ltc1702a no r sense 2-phase dual synchronous step-down 550khz, no sense resistor controller ltc1708-pg 2-phase, dual synchronous controller with mobile vid 3.5v v in 36v, vid sets v out1 , pgood lt1709/ high efficiency, 2-phase synchronous step-down 1.3v v out 3.5v, current mode ensures lt1709-8 switching regulators with 5-bit vid accurate current sharing, 3.5v v in 36v ltc1735 high efficiency synchronous step-down output fault protection, 16-pin ssop switching regulator ltc1778/ltc1778-1 no r sense current mode synchronous step-down up to 97% efficiency, 4v v in 36v, 0.8v v out (0.9)(v in ), controllers i out up to 20a ltc1929/ 2-phase synchronous controllers up to 42a, uses all surface mount components, ltc1929-pg no heat sinks, 3.5v v in 36v ltc3708 dual, 2-phase, dc/dc controller with output tracking current mode, no r sense , up/down tracking, synchronizable ltc3711 no r sense current mode synchronous step-down up to 97% efficiency, ideal for pentium ? iii processors, controller with digital 5-bit interface 0.925v v out 2v, 4v v in 36v, i out up to 20a ltc3728 dual, 550khz, 2-phase synchronous step-down dual 180 phased controllers, v in 3.5v to 35v, 99% duty cycle, controller 5x5qfn, ssop-28 ltc3729 20a to 200a, 550khz polyphase synchronous controller expandable from 2-phase to 12-phase, uses all surface mount components, v in up to 36v ltc3731 3- to 12-phase step-down synchronous controller 60a to 240a output current, 0.6v v out 6v, 4.5v v in 32v ltc3770 fast, no r sense step-down synchronous controller 0.67% 0.6v reference voltage; programmable margining; true with margining, tracking, pll current mode; 4v v in 32v no r sense and polyphase are trademarks of linear technology corporation. pentium is a registered trademark of intel corporation. related parts u typical applicatio figure 16. multioutput polyphase application linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt/tp 0405 500 ?printed in usa phasmd clkout tg1 tg2 0 i 1 i 3 i 2 i 4 90 open 180 u1 ltc3729 buck: 2.5v/15a buck: 2.5v/15a pllin tg1 tg2 90 90 270 u2 ltc3828 buck: 1.5v/15a 2.5v o /30a c in i in 12v in *input ripple current cancellation increases the ripple frequency and reduces the rms input ripple current thus, saving input capacitors i in * 1.5v o /15a 1.8v o /15a 3828 f16 buck: 1.8v/15a i 1 i 2 i 3 i 4

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